1. Field of the Invention
The present invention is directed to the design and manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to a method of estimating path delays for static timing analysis of an integrated circuit design.
2. Description of Related Art
Static timing analysis (STA) is generally used to anticipate timing problems in an integrated circuit design before committing the design to silicon. In typical static timing analysis, the worst-case stage delay is estimated for each stage of each net in the design and added together to estimate the net delay for each net.